The present invention concerns memory circuits and clock-generation circuits which include delay-locked loops for controlling memory circuits.
Memory circuits are vital components in computers and other electronic systems which require data storage. A typical memory circuit is an interconnected network of millions of microscopic memory cells, each of which stores an electric charge representing a one or zero data bit. The memory cells are usually arranged into rows and columns, with each cell having a unique address based on its row and column position.
Memory operations, usually initiated by a computer processor, include writing and reading the memory cells. In writing, sometimes called recording or programming, the processor sends command signals specifying a write operation, address signals identifying one or more memory cells, and data signals representing the data to be stored, or written to, the one or more memory cells. The memory circuit has circuitry not only for latching, that is, temporarily storing current signal states, but also for interpreting, or decoding, the command signals. Once the latched command signals are decoded, the memory circuit addresses, or accesses, the memory cells corresponding to the latched address signals and writes the latched data signals to them.
To read data, the processor sends command signals which specify a read operation and address signals which identify the memory cells to be read to the memory circuit. After latching the command and address signals, the memory circuit accesses the identified memory cells, converts their contents to data signals, latches the data signals, and finally outputs the latched data signals to the computer processor.
In both reading and writing, the latching, decoding, addressing, and outputting are all sequenced using clock signalsxe2x80x94typically signals with a series of periodic or regularly spaced pulsesxe2x80x94which coordinate the flow of signals into, through, and out of the memory circuit. Coordination often requires triggering one operation a certain time after another operation.
For example, during write operations, data signals are usually transferred, one word (a group of data bits) at a time, from a computer processor to a memory circuit using a clock signal to control when each word is sent. The sending of each word corresponds to a clock signal transition from high to low (or low to high), and the data signals travel over a set of wires, known as a data bus, connecting the processor to the memory circuit. As the data signals for one word arrive at input terminals of the memory circuit, the voltages of the input terminals change from their current voltage levels (which generally represent the previous word) to those for the current word. After this change, a latch circuit, triggered with the high-to-low (or low-to-high) transition of another clock, latches the data signals for the current word. To allow time for the change, the other clock signal is usually a delayed version of the data clock, with its transitions occurring a set time, or delay period, after those of the data clock.
Since writing entails a number of sequential operations that are delayed relative the data clock, memory circuits typically use several different delayed versions of the data clock. For instance, a memory circuit might include a set of clock signals delayed one, two, three, and four delay periods relative the data clock, with each of the delayed clock signals controlling a different part of the memory circuit.
One way of generating a set of delayed clock signals based on multiples of a delay period is to use a circuit known as a delay-locked loop, or DLL. The delay-locked loop is a chain of controllable delay elements, with the first delay element receiving an input clock signal and outputting a clock signal delayed one delay period, the second receiving this delayed clock signal and outputting a signal delayed two delay periods relative the input clock signal, and so forth. To ensure that each delayed clock signal is synchronized, or phase-locked, with the transitions of the input clock signal, a phase comparator compares one of the delayed clock signals to the input clock signal, and outputs a control signal, based on how far it is out of synch, to all the delay elements, decreasing or increasing their delays as necessary to keep all the delayed clock signals in step, or in phase, with the input clock.
As memory circuits have become faster, it has become increasingly difficult to design delay-locked loops which produce signals with smaller and smaller delays relative to a clock signal, such as the data clock. This is because conventional delay elements can only reliably provide a minimum delay of about 100 picoseconds (one-tenth of one billionth of a second.) To provide smaller delays, engineers have added xe2x80x9ctiersxe2x80x9d of interpolation circuitry to the basic delay-locked loop.
A first tier of the interpolation circuitry theoretically interpolates, or splits, the 100-picosecond difference between two signals of the delay-locked loop to produce a third signal delayed 50 picoseconds relative the two signals. A second tier of interpolation circuitry then splits the 50 picosecond difference between the third signal and one of the two original signals to produce a fourth signal delayed 25 picoseconds relative the one original signal. Using this interpolation approach in a non-memory application, one researcher reports achieving delays as small as 16 picoseconds. (See, T. A. Knotts and D. S. Chu, xe2x80x9cA 500 MHZ Time Digitizer IC with 15.625 ps Resolution,xe2x80x9d 1994 IEEE International Solid State Circuits Conference, Digest of Technical Papers, First Edition, pp. 58-59.)
Unfortunately, this interpolation approach not only adds a significant amount of circuitry to the basic delay-locked loop, but also increases power considerably. Thus, there is a need for a better way of achieving shorter delay periods between clock signals.
To address these and other needs, the inventor devised new clock-generation circuits and new methods of generating clock signals. One embodiment of a new clock-generation circuit interlaces and synchronizes two delay-locked loops. Each delay-locked loop includes a number of controllable delay elements linked in a chain. The first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal. In addition, at least one delay element in the second loop is controlled based on a phase relationship between clock signals from each loop.
One embodiment of a method of generating clock signals entails generating a sets of even and odd clock signals, with each even clock signal delayed relative a reference clock signal by an even multiple of a desired delay period and each odd clock signal delayed relative the reference clock signal by an odd multiple of the desired delay period. The method also entails synchronizing at least one of the odd clock signals using one of the even clock signals.
Other aspects of the invention include a memory controller that incorporates one of the new clock-generation circuits and a computer system that incorporates the memory controller. One embodiment of the computer system includes a processor, and one or more synchronous dynamic random access memories (SDRAMs).